Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate structure is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-type and p-type (NMOS and PMOS) transistors are used to fabricate logic and other circuitry.
The source and drain regions of a MOS are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, having a gate dielectric located over the channel and a gate conductor above the gate dielectric. The gate dielectric is an insulator material, which prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing such an applied gate voltage to set up a transverse electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or by growing silicon dioxide (SiO2) or silicon oxynitride (SiON) over a silicon wafer surface, with doped polysilicon formed over the SiO2 to act as the gate conductor.
Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate conductor of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate dielectric that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which the thickness of SiO2 gate dielectrics can be reduced. For example, thin SiO2 gate dielectrics are prone to gate tunneling leakage currents resulting from direct tunneling of electrons through the thin gate dielectric. In addition, there are conventional limitations on the ability to form thin dielectric films with uniform thickness. Furthermore, thin SiO2 gate dielectric layers provide a poor diffusion barrier to dopants and may allow high boron dopant penetration from the p+ polysilicon gate into the underlying channel region of the semiconductor substrate during fabrication of the source/drain regions.
Recent MOS and CMOS transistor scaling efforts have accordingly focused on high-k dielectric materials having dielectric constants greater than that of SiO2 (e.g., greater than about 3.9), which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. The relative electrical performance of such high-k dielectric materials is often expressed as equivalent oxide thickness (EOT), because the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Since the dielectric constant “k” is higher than silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO2.
Hafnium based High-K/Metal Gate stacks are one alternative to SiON/Poly-Si gate stacks. Although high-K dielectrics offer significant scaling with respect to SiON, on account of their higher dielectric constant, the effect of the dielectric constant of these gate stacks is tempered by. the thermodynamically favored growth of a low dielectric constant SiO2-like interface layer between the hafnium based high-k gate dielectric and the silicon based substrate, on which the hafnium based high-k gate dielectric is typically formed.
Apart from the scaling drawback, polysilicon gates of high-k gate dielectrics have also been shown to exhibit “Fermi-level pinning”, a phenomenon due to which the threshold voltages for nFETs and pFETs are both high. In order to solve this issue, several groups have proposed a dual-metal gate approach. This approach, however, is beset by the issue of metal gate patterning. To pattern the gate stacks, the photoresist needs to be deposited directly on the metal gate and after development and etching, removed without damaging the gate stack. Photoresist removal is typically performed using an oxygen ash process. The oxygen ash process, however, adds to the thickness of the SiO2-like interface layer by providing oxygen that could flow laterally into the gate stack.